ASIC Design Tutor
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Job summary
Amazing Properties is looking for an experienced ASIC design tutor to join us as a one-on-one online tutor. You will teach the full digital chip design flow, from RTL development to tapeout preparation.
Min Qualification:
Degree
Experience Level:
Mid level
Experience Length:
4 years
Language Requirement:
English
Work Type:
Full Time
Working Hours:
8 to 5
Applicant Location:
Remote
Job descriptions & requirements
Responsibilities:
- Teach students how to develop, enhance, and debug VHDL and Verilog/SystemVerilog code for chip designs.
- Train students to verify design functionality on HDL simulators such as ModelSim, QuestaSim, or Xcelium, and to run synthesis with Synopsys or Cadence Genus.
- Teach clock domain crossing (CDC) and reset domain crossing (RDC) verification.
- Teach Design for Test (DFT), including adding memory BIST and JTAG scan chains to a design.
- Guide students in developing and porting RTL to an FPGA prototyping board.
- Teach place and route of the netlist before tapeout, including clock tree synthesis (CTS).
- Train students to run static timing analysis (STA) and power analysis after CTS and place and route.
- Cover packaging and evaluation board requirements for the physical chip.
- Develop training materials, labs, and practical exercises, and adapt lessons to each student's skill level and goals.
Requirements:
- Proven experience developing in VHDL and Verilog (or SystemVerilog).
- Experience targeting VHDL designs to Xilinx FPGAs.
- Experience using ModelSim/QuestaSim.
- Experience using Cadence Virtuoso.
- Working knowledge of synthesis, CDC/RDC, DFT, place and route, CTS, and STA.
- Strong communication skills and the ability to explain complex technical concepts clearly.
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